(1) Field of the Invention
The present invention relates to a method for making integrated circuits on semiconductor substrates, and more particularly to a method for forming multilevel wiring on substrates using a hybrid low-k (low dielectric constant) intermetal dielectric (IMD) layer that reduces the RC time delays. The method is particularly useful when the minimum feature sizes are less than 0.25 micrometer (um) and the interconnect delays become greater than the field effect transistor (FET) gate delays.
(2) Description of the Prior Art
As the Ultra Large Scale Integration (ULSI) circuit density increases and device features sizes become less than 0.25 micrometers, increasing numbers of patterned metal levels are required with decreasing spacings between metal lines at each level to effectively wire up discrete semiconductor devices on the semiconductor chips. In the more conventional method the different levels of metal interconnections are separated by layers of insulating material. These interposed insulating layers have etched via holes which are used to connect one level of metal to the next. Typically, the insulating layer is a silicon oxide (SiO.sub.2) having a dielectric constant k (relative to vacuum) of about 4.1 to 4.5.
However, as the device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between the metal lines at each level of interconnections to effectively wire up the integrated circuits. Unfortunately, as the spacing decreases, the intra- (on the same metal level) and interlevel (between metal levels) capacitances increase between metal lines since the capacitance C is inversely proportional to the spacing d between the lines (C=keA/d where k is the dielectric coefficient, e is the vacuum permittivity, A is the area, and d is the spacing between lines). Therefore, it is desirable to minimize the dielectric constant k in the insulator (dielectric) between the conducting lines to reduce the RC time constant and thereby increase the performance of the circuit (frequency response) since the signal propagation time in the circuit is adversely affected by the RC delay time, where R is the resistance of the metal line, and C is the inter- and/or the intralevel capacitance mentioned above.
To achieve an insulating layer with a dielectric constant less than 3.0, relatively porous spin-on insulating films are commonly used, such as hydrogen silsesquioxane (a Si polymer) (HSQ) with a k of 2.7-3.0, and other spin-on insulators commonly referred to as aerogels, nanogels or nanofoams. However, these low-k insulators are usually very porous and therefore do not provide good structural support for integration. Further, absorbed moisture and other chemicals in the porous insulator can cause corrosion of the metal lines.
Several methods for forming planarized interconnections using low-dielectric-constant insulators have been described. For example, in U.S. Pat. Nos. 5,476,817 and 5,510,293 to Numata, a conformal thermoconductive insulating layer, such as AlN, is deposited over the metal lines. A low-dielectric constant, such as an organic spin-on glass (OSOG), is deposited between the metal lines to reduce capacitance. Then another thermoconductive insulating layer is deposited over the metal lines and the low-k material. Another method is described in U.S. Pat. No. 5,759,906 to Lou in which a low-k spin-on layer is used to reduce capacitance and a fluorine-doped SiO.sub.2 is deposited to form protective sidewalls in via holes to prevent corrosion of the metal from the low-k spin-on layer. Ahlburn et al. in U.S. Pat. No. 5,607,773 form a conformal protective layer composed of SiO.sub.2 over the metal lines and then a low-k HSQ layer is deposited by spin coating and is cured. The multilevel dielectric is then completed by depositing a CVD SiO.sub.2 or fluorine-doped silicon glass by adding CF.sub.4 during deposition. U.S. Pat. Nos. 5,668,398 and 5,461,003 to Havemann et al. describe a method for making multilevel interconnections with air gaps formed between the metal lines. The methods involve exposing a disposable material between metal lines to O.sub.2 through a porous oxide. The volatilized disposable material is then removed through the porous oxide to form an air gap with a dielectric constant of about 1.
Therefore there is still a need in the semi-conductor industry to provide an improved hybrid low-k intermetal dielectric that minimizes inter- and intralevel capacitance to reduce the RC time constant while providing a more reliable and manufacturable process.